NXP Semiconductors /LPC13Uxx /SYSCON /SYSAHBCLKCTRL

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Interpret as SYSAHBCLKCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RESERVED)SYS 0 (DISABLE)ROM 0 (DISABLE)RAM0 0 (DISABLED)FLASHREG 0 (DISABLED)FLASHARRAY 0 (DISABLE)I2C 0 (DISABLE)GPIO 0 (DISABLE)CT16B0 0 (DISABLE)CT16B1 0 (DISABLE)CT32B0 0 (DISABLE)CT32B1 0 (DISABLE)SSP0 0 (DISABLE)USART 0 (DISABLE)ADC 0 (DISABLE)USB 0 (DISABLE)WWDT 0 (DISABLE)IOCON 0RESERVED 0 (DISABLE)SSP1 0 (DISABLE)PINT 0RESERVED 0 (DISABLE)GROUP0INT 0 (DISABLE)GROUP1INT 0RESERVED 0 (DISABLE)RAM1 0 (DISABLE)USBSRAM 0RESERVED

CT32B1=DISABLE, GROUP1INT=DISABLE, WWDT=DISABLE, RAM0=DISABLE, USB=DISABLE, PINT=DISABLE, FLASHARRAY=DISABLED, SSP1=DISABLE, GPIO=DISABLE, ADC=DISABLE, SYS=RESERVED, ROM=DISABLE, IOCON=DISABLE, USBSRAM=DISABLE, RAM1=DISABLE, SSP0=DISABLE, CT16B0=DISABLE, FLASHREG=DISABLED, GROUP0INT=DISABLE, CT32B0=DISABLE, USART=DISABLE, CT16B1=DISABLE, I2C=DISABLE

Description

System clock control

Fields

SYS

Enables the clock for the AHB, the APB bridge, the Cortex-M3 FCLK and HCLK, SysCon, and the PMU. This bit is read only and always reads as 1.

0 (RESERVED): Reserved

1 (ENABLE): Enable

ROM

Enables clock for ROM.

0 (DISABLE): Disable

1 (ENABLE): Enable

RAM0

Enables clock for SRAM0.

0 (DISABLE): Disable

1 (ENABLE): Enable

FLASHREG

Enables clock for flash register interface.

0 (DISABLED): Disabled

1 (ENABLED): Enabled

FLASHARRAY

Enables clock for flash array access.

0 (DISABLED): Disabled

1 (ENABLED): Enabled

I2C

Enables clock for I2C.

0 (DISABLE): Disable

1 (ENABLE): Enable

GPIO

Enables clock for GPIO port registers.

0 (DISABLE): Disable

1 (ENABLE): Enable

CT16B0

Enables clock for 16-bit counter/timer 0.

0 (DISABLE): Disable

1 (ENABLE): Enable

CT16B1

Enables clock for 16-bit counter/timer 1.

0 (DISABLE): Disable

1 (ENABLE): Enable

CT32B0

Enables clock for 32-bit counter/timer 0.

0 (DISABLE): Disable

1 (ENABLE): Enable

CT32B1

Enables clock for 32-bit counter/timer 1.

0 (DISABLE): Disable

1 (ENABLE): Enable

SSP0

Enables clock for SSP0.

0 (DISABLE): Disable

1 (ENABLE): Enable

USART

Enables clock for UART.

0 (DISABLE): Disable

1 (ENABLE): Enable

ADC

Enables clock for ADC.

0 (DISABLE): Disable

1 (ENABLE): Enable

USB

Enables clock to the USB register interface.

0 (DISABLE): Disable

1 (ENABLE): Enable

WWDT

Enables clock for WWDT.

0 (DISABLE): Disable

1 (ENABLE): Enable

IOCON

Enables clock for I/O configuration block.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

SSP1

Enables clock for SSP1.

0 (DISABLE): Disable

1 (ENABLE): Enable

PINT

Enables clock to GPIO Pin interrupts register interface.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

GROUP0INT

Enables clock to GPIO GROUP0 interrupt register interface.

0 (DISABLE): Disable

1 (ENABLE): Enable

GROUP1INT

Enables clock to GPIO GROUP1 interrupt register interface.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

RAM1

Enables clock for SRAM1 located at 0x2000 0000 to 0x2000 0800.

0 (DISABLE): Disable

1 (ENABLE): Enable

USBSRAM

Enables USB SRAM block located at 0x2000 4000 to 0x2000 4800.

0 (DISABLE): Disable

1 (ENABLE): Enable

RESERVED

Reserved

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